In a multi-clock design, metastability cannot be avoided but the adverse effects of metastability can be neutralized. Due to setup/hold timing violations at the first flop in destination domain, this flop could go into a metastable state, thus, causing chances of failure. Simply put, a metastable state is a state where a signal is neither at level 0 or level 1 i.e. Metastability is the most common issue which could arise due to CDC. What is metastability & Why it is dangerous? In this case, the phase difference between C1 & C2 is not known and it is uncertain so, CDC occurs even if C1 & C2 are of same frequency Clock C1 & C2 are from two different source.Example 50 & 37 Mhz clocks generated form the same source Clock C1 & C2 are from the same source but their phase varies over the time.When data crosses from one clock domain to the other, it is called as Clock Domain Crossing (CDC). CLK, its inversion and D1 (derived from CLK) are synchronous to each other.Ī clock domain crossing occurs whenever data is transferred from a flop driven by one clock to a flop driven by another clock. Figure 1 illustrates three different clocks in a design, but synchronous to each other. But, 50MHz and 37MHz clocks (whose phase relationship changes over time) define two separate clock domains. For example, a clock and its derived clock (via a clock divider) are in the same clock domain because they have a constant phase relationship. Conversely, domains that have clocks with variable phase and time relationships are considered different clock domains.Ī clock domain is a part of a design that has a clock that operates asynchronous to, or has a variable phase relationship with, another clock in the design. A clock and its inverted clock or its derived divide-by-two clocks are considered a clock domain (synchronous).
A clock domain is defined as that part of the design driven by either a single clock or clocks that have constant phase relationships over the time.